CMOS#

Complementary Metal (Poly-Si) Oxide (SiO2) Semiconductor (CMOS).

NOT	NAND	NOR

Parameters#


channel width	$W_{\ir n/p}$
channel length	$L_{\ir n/p}$
gate oxide thickness	$t_{\ir ox}$
electron mobility	$\mu_{\ir n} \approx \SI{250e-4}{\meter\squared\per\volt\second}$
	$\mu_{\ir p} \approx \SI{200e-4}{\meter\squared\per\volt\second}$
rel. permittivity of gate oxide	$\epsilon_{\ir ox} \approx 3,9$
dielectric constant	$\epsilon_0 = \SI{8.8541878e-12}{\ampere\second\per\volt\meter}$
specific oxide capacity	$C'_{\ir ox} = \frac{\varepsilon_{\ir ox} \varepsilon_0}{t_{\ir ox}}$
oxide capacity	$C_{\ir ox} = C'_{\ir ox} \cdot WL$
gain (also $\beta$)	$K_{\ir n} = \mu_{\ir n} C'_{\ir ox} \frac{W_{\ir n}}{L_{\ir n}}$
	$K_{\ir p} = (-1) \mu_{\ir p} C'_{\ir ox} \frac{W_{\ir p}}{L_{\ir p}}$
propagation delay	$t_{\ir pHL} \propto \frac{C_L t_{\ir ox} L_{\ir p}}{W_{\ir p} \mu_{\ir p} \varepsilon_{\ir ox} (V_{\ir DD} -

Power Consumption of a CMOS Inverter

\[P_{\ir dyn} = P_{\ir cap} + P_{\ir short}\]

\[P_{\ir cap} = \alpha_{01} f C_L V_{\ir DD}^2\]

\[P_{\ir short} = \alpha_{01} f \beta_n \tau (V_{\ir DD} - 2V_{\ir th})^3\]


channel width	\(W_{\ir n/p}\)
channel length	\(L_{\ir n/p}\)
gate oxide thickness	\(t_{\ir ox}\)
electron mobility	\(\mu_{\ir n} \approx \SI{250e-4}{\meter\squared\per\volt\second}\)
	\(\mu_{\ir p} \approx \SI{200e-4}{\meter\squared\per\volt\second}\)
rel. permittivity of gate oxide	\(\epsilon_{\ir ox} \approx 3,9\)
dielectric constant	\(\epsilon_0 = \SI{8.8541878e-12}{\ampere\second\per\volt\meter}\)
specific oxide capacity	\(C'_{\ir ox} = \frac{\varepsilon_{\ir ox} \varepsilon_0}{t_{\ir ox}}\)
oxide capacity	\(C_{\ir ox} = C'_{\ir ox} \cdot WL\)
gain (also \(\beta\))	\(K_{\ir n} = \mu_{\ir n} C'_{\ir ox} \frac{W_{\ir n}}{L_{\ir n}}\)
	\(K_{\ir p} = (-1) \mu_{\ir p} C'_{\ir ox} \frac{W_{\ir p}}{L_{\ir p}}\)
propagation delay	$t_{\ir pHL} \propto \frac{C_L t_{\ir ox} L_{\ir p}}{W_{\ir p} \mu_{\ir p} \varepsilon_{\ir ox} (V_{\ir DD} -